For the manufacture of a semiconductor device, an element isolation region is formed in a semiconductor substrate, a semiconductor element such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed in each active region of the semiconductor substrate defined by the element isolation region, and a multilayer wiring structure is formed over the semiconductor substrate. Further, a technique using a SOI substrate as the semiconductor substrate has also been known.
Japanese Unexamined Patent Application Publication No. 2002-9144 (Patent Document 1), Japanese Unexamined Patent Application Publication No. 2004-363121 (Patent Document 2), Japanese Unexamined Patent Application Publication No. 2006-222329 (Patent Document 3) and Japanese Unexamined Patent Application Publication No. 2007-526652 (Patent Document 4) describe a technique relating to a semiconductor device including a STI (Shallow Trench Isolation).